Download: ZYNQ Training - session 07 part IV - Coding an AXI Stream Module in Verilog

By Mohammadsadegh Sadri


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In this video, we focus on the the design of "SampleGenerator" AXI stream block. We have already talked about the functionality and interfaces of this block in previous videos of this session.
In this session we begin writing a verilog RTL code for this axi stream block.